- Instructor: Dr. J.C. Huang.
- Class meets: Mondays, Wednesdays, 1:00 - 2:30 PM, 211 PGH.
- Official Class web page: http://www.cs.uh.edu/~jhuang/JCH/LD/3410.html.
- Lab and Study Aid: http://www134.pair.com/trapdoor/cs3410/ created by Adila Esbhani who can be reached at cs3410@hotmail.com.
- Lab sessions and lab instructors:
Sections 07176 / 07178 / 07180 meet MW 2:30-4PM / 4-5:30PM / 5:30-7PM, T. Mark Huang (tihuang at cs . uh . edu)
Other lab sections 07177 / 11053 meet TTH 11:30AM-1PM / 1-2:30PM, Kaushik Nagabhushan (kaushikn at cs . uh . edu).- Text Book: Fundamentals of Digital Logic with VHDL Design, by Stephen Brown and Zvonko Vranesic (McGraw-Hill). And you can get Errata for both textbook and code in the CDROM.
- Lab location: 533 PGH. You have to enter the lab through 547 PGH.
Last modified: May 05, 2000. tihuang at cs . uh . eduAnnouncement
Labs
Grading
Helpful info for this course
Here are some materials which will help you go through this course.
(02/17/2000)