Experiments

Experiment #7 Sample Gated D Latch Waveform

This is the simulation of the gated D latch. You should start all simulations by first clearing the latch. This essentially initializes the latch so that it immediately assumes some state. Notice that when the clock is 0, D has no effect on Q (110ns to 180ns); however, when the clock is 1, Q follows D (180 to 250ns). This is what is meant by level sensitive.