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Spring 2000
Computer Science 3410 - Lab Information
Design Entry using VHDL
Open a new project and save it as VHDL1.
Here is some VHDL code for a very simple function F = (a' + b)(c + d)
ENTITY VHDL1 IS
PORT ( a, b, c, d : IN BIT;
F : OUT BIT);
END VHDL1;
ARCHITECTURE LogicFunc OF VHDL1 IS
BEGIN
f <= (NOT a OR b) AND (c OR d);
END LogicFunc;
Remember that you must use parenthesis as VHDL does not recognize any precedence of logical operators.
You can use any text editor or the one supplied in MAX+plusII (MAX+plusII -> Text Editor). Save the file as VHDL1.vhd (not .tdf)
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